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LCX020BK
1.8cm (0.7-inch) Color LCD Panel
Description The LCX020BK is a 1.8cm diagonal active matrix TFT-LCD panel addressed by polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. This panel provides full-color representation. RGB dots are arranged in a striped pattern optimum for data applications and capable of displaying fine text and vertical lines. The adoption of an advanced on-chip black matrix realizes a high luminance screen, and high picture quality is possible with built-in cross talk free and ghost free circuits. This panel has a polysilicon TFT high-speed scanner and built-in function to display images up/down and/or right/left inverse. In addition, the built-in 5V interface circuit leads to lower voltage of timing and control signals. The panel contains a display area varying circuit which supports Macintosh161/SVGA/VGA/PC982 data signals by changing the display area according to the type of input signal. In addition, double-speed processed NTSC/PAL/WIDE can also be supported. 1 "Macintosh" is a trademark of Apple Company Inc. 2 "PC98" is a trademark of NEC. Features * Number of active dots: 1,557,000, 1.8cm (0.7-inch) in diagonal * Supports Macintosh16 (832 x 624), SVGA (800 x 600), VGA (640 x 480) and PC98 (640 x 400) display * Supports NTSC (640 x 480), PAL (762 x 572) and WIDE (832 x 480) display by processing the video signal at double speed * High optical transmittance: 1% (typ.) * Built-in cross talk free circuit * High contrast ratio with normally white mode: 70 (typ.) * Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible) * Up/down and/or right/left inverse display function Element Structure * Dots: 2496 (H) x 624 (V) = 1,557,504 * Built-in peripheral driving circuit using polycrystalline silicon super thin film transistors Applications * Liquid crystal EVFs for personal PCs/DVDs * Small monitors, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E99210-PS
V Shift Register (Bidirectional Scanning)
Precharge Control Circuit
Black Frame Control Circuit
Black Frame Control Circuit
V Shift Register (Bidirectional Scanning)
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2 3 4
PSIGR PSIGG PSIGB
Up/Down and/or Right/Left Inversion Control Circuit HST HCK1 HCK2 BLK RGT VST VCK PCG DWN ENB MODE1 MODE2 MODE3 HVDD VVDD VSS
28 29 30 32 Input Signal Level Shifter Circuit H Shift Register (Bidirectional Scanning) Black Frame Control Circuit
Block Diagram The Block Diagram of the panel is shown below.
24 35 34 37 36 33 27 26 25 23 38 31 5 6 7 8
SIGR1 SIGR2 SIGR3 SIGR4 SIGR5 SIGR6 SIGG1 SIGG2 SIGG3 SIGG4 SIGG5 SIGG6 SIGB1 SIGB2 SIGB3 SIGB4 SIGB5 SIGB6 COM
9 10 11 12 13 14 15 16 17 18 19 20 21 22 1
COM Pad
LCX020BK
LCX020BK
Absolute Maximum Ratings (Vss = 0V) * H driver supply voltage HVDD * V driver supply voltage VVDD * Common pad voltage COM * H shift register input pin voltage HST, HCK1, HCK2, RGT * V shift register input pin voltage VST, VCK, PCG, BLK, ENB, DWN MODE1, MODE2, MODE3 * Video signal input pin voltage SIGR1 to SIGR6, SIGG1 to SIGG6, SIGB1 to SIGB6, PSIGR, PSIGG, PSIGB * Operating temperature Topr * Storage temperature Tstg
-1.0 to +20 -1.0 to +20 -1.0 to +17 -1.0 to +17 -1.0 to +17
V V V V V
-1.0 to +15
V
-10 to +70 -30 to +85
C C
Operating Conditions (Vss = 0V) * Supply voltage 15.5 0.3V HVDD VVDD 15.5 0.3V * Input pulse voltage (Vp-p of all input pins except video signal and uniformity improvement signal input pins) Vin 5.0 0.5V
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Symbol COM PSIGR PSIGG PSIGB SIGR1 SIGR2 SIGR3 SIGR4 SIGR5 SIGR6 SIGG1 SIGG2 SIGG3 SIGG4 Common voltage of panel Uniformity improvement signal input (R) Uniformity improvement signal input (G) Uniformity improvement signal input (B) Video signal input to panel (R-1) Video signal input to panel (R-2) Video signal input to panel (R-3) Video signal input to panel (R-4) Video signal input to panel (R-5) Video signal input to panel (R-6) Video signal input to panel (G-1) Video signal input to panel (G-2) Video signal input to panel (G-3) Video signal input to panel (G-4) -3- Description
LCX020BK
Pin No. 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Symbol SIGG5 SIGG6 SIGB1 SIGB2 SIGB3 SIGB4 SIGB5 SIGB6 HVDD RGT MODE3 MODE2 MODE1 HST HCK1 HCK2 VSS BLK ENB VCK VST DWN PCG VVDD SOUT Video signal input to panel (G-5) Video signal input to panel (G-6) Video signal input to panel (B-1) Video signal input to panel (B-2) Video signal input to panel (B-3) Video signal input to panel (B-4) Video signal input to panel (B-5) Video signal input to panel (B-6) Power supply input for H driver
Description
Drive direction input for H shift register (H: normal, L: reverse) Display area switching 3 input Display area switching 2 input Display area switching 1 input Start pulse input for H shift register drive Clock pulse input for H shift register drive Clock pulse input for H shift register drive GND (H, V drivers) Black frame display pulse input Gate selection pulse enable input Clock pulse input for V shift register drive Start pulse input for V shift register drive Drive direction input for V shift register (H: normal, L: reverse) Uniformity improvement pulse input Power supply input for V driver H and V shift register drive checking (Test pin; no connection.)
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LCX020BK
Input Equivalent Circuits To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition, protective resistors are added to all pins except video signal inputs. All pins are connected to Vss with a high resistance of 1M (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)
(1) SIGR1 to SIGR6, SIGG1 to SIGG6, SIGB1 to SIGB6, PSIGR, PSIGG, PSIGB
HVDD
Input 1M
Signal line
(2) HCK1, HCK2
HVDD 250 250 Level conversion circuit (2-phase input) 1M 250 1M
Input
250
(3) RGT, MODE1, MODE2, MODE3
HVDD 2.5k Input 1M 2.5k Level conversion circuit (single-phase input)
(4) HST
Input
HVDD 250 250 Level conversion circuit (single-phase input)
1M
(5) PCG, VCK
Input
VVDD 250 250 Level conversion circuit (single-phase input)
1MW
(6) VST, BLK, ENB, DWN
VVDD 2.5k 2.5k Level conversion circuit (single-phase input)
Input 1M
(7) COM
VVDD
Input 1M LC
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LCX020BK
Input Signals 1. Input signal voltage conditions (Vss = 0V) Item H shift register input voltage (Low) HST, HCK1, HCK2, RGT (High) V shift register input voltage (Low) MODE1, MODE2, MODE3, BLK, VST, VCK, PCG, (High) ENB, DWN Video signal center voltage Video signal input range1 Common pad voltage of panel2 Uniformity improvement signal input voltage (PSIGR, PSIGG, PSIGB)3 Symbol VHIL VHIH VVIL VVIH VVC Vsig Vcom Vpsig1 Vpsig2 Min. -0.5 4.5 -0.5 4.5 6.9 VVC - 4.5 VVC - 0.5 VVC 2.0 VVC 4.0 Typ. 0.0 5.0 0.0 5.0 7.0 7.0 VVC - 0.4 VVC 3.0 VVC 4.5 Max. 0.4 5.5 0.4 5.5 7.1 VVC + 4.5 VVC - 0.3 VVC 4.0 VVC 4.6 Unit V V V V V V V V V
1 Video input signal shall be symmetrical to VVC. 2 The optimum typical value of the common pad voltage may lower its suitable voltage according to the set construction to use. In this case, use the voltage of which has maximum contrast as typical value. When the typical value is lowered, the maximum and minimum values may lower. 3 Input a uniformity improvement signals PSIGR, PSIGG and PSIGB in the same polarity with video signals SIGR1 to 6, SIGG1 to 6 and SIGB1 to 6 and which is symmetrical to VVC. PSIGR, PSIGG and PSIGB have two steps as shown by the waveform in the figure below, and in the table above, the upper value indicates the signal level of the first step, and the lower value, the signal level of the second step. Here, the rising and falling of PSIGR, PSIGG and PSIGB are synchronized with the rising of PCG pulse, and the rise and fall times trPSIGR, trPSIGG, trPSIGB, tfPSIGR, tfPSIGG and tfPSIGB are suppressed within 800ns. Input waveform of uniformity improvement signal PSIG
PRG
90% PSIGR, PSIGG, PSIGB
Vpsig2 VVC
Vpsig1 10%
trPSIGR, trPSIGG, trPSIGB
tfPSIGR, tfPSIGG, tfPSIGB
LCX020BK level conversion circuit The LCX020BK has a built-in level conversion circuit in the clock input unit on the panel. The input signal level increases to HVDD or VVDD. The Vcc of external ICs are applicable to 5 0.5V. -6-
LCX020BK
2. Clock timing conditions (Ta = 25C) Item Hst rise time HST Hst fall time Hst data setup time Hst data hold time Hckn rise time4 HCK Hckn fall time4 Hck1 fall to Hck2 rise time Hck1 rise to Hck2 fall time Vst rise time VST Vst fall time Vst data setup time Vst data hold time VCK Vck rise time Vck fall time Enb rise time Enb fall time ENB Vck rise/fall to Enb rise time Horizontal video period end to Enb fall time Enb fall to Pcg rise time Pcg rise time Pcg fall time PCG Pcg rise to Prg rise time Pcg fall to Prg fall time Pcg rise to Vck rise/fall time Pcg pulse width Blk rise time BLK5 Blk fall time Blk fall to Vst rise time Blk pulse width
(Macintosh16 mode: fHckn = 4.8MHz, fVck = 24.9kHz) Symbol trHst tfHst tdHst thHst trHckn tfHckn to1Hck to2Hck trVst tfVst tdVst thVst trVck tfVck trEnb tfEnb toEnb tdEnb toPcg trPcg tfPcg toPrgr toPrgf toVck twPcg trBlk tfBlk toVst twBlk Min. -- -- 70 15 -- -- -15 -15 -- -- 5 5 -- -- -- -- 400 900 900 -- -- 0 200 0 1100 -- -- 1 1 Typ. -- -- 80 25 -- -- 0 0 -- -- 10 10 -- -- -- -- 500 1000 1000 -- -- -- 250 1000 1200 -- -- -- -- Max. 30 30 90 35 30 30 15 15 100 100 15 15 100 100 100 100 -- -- -- 30 30 -- -- 1100 1300 100 100 2 -- line ns s ns Unit
4 Hckn means Hck1 and Hck2. 5 Blk is the timing during SVGA mode (fHckn = 4.0MHz, fVck = 24.0kHz). This pulse is positive polarity other than in Macintosh16 mode. Set to L level in Macintosh16 mode.
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LCX020BK
Item Hst rise time Hst fall time HST Symbol trHst
Hst 10% trHst 6
Waveform
90% 90% 10% tfHst
Conditions * Hckn3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns
tfHst
Hst data setup time
tdHst
50% Hst Hck1
50%
Hst data hold time
thHst
tdHst
50%
50% thHst 90% 10%
* Hckn3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns
Hckn rise time3 Hckn fall time3 HCK
trHckn
90% 3 Hckn 10%
tfHckn
6
* Hckn3 duty cycle 50% to1Hck = 0ns to2Hck = 0ns
trHckn
tfHckn
Hck1 fall to Hck2 rise time
50%
50%
to1Hck
Hck1
50%
50%
Hck1 rise to Hck2 fall time 6 Definitions: The right-pointing arrow ( The left-pointing arrow ( The black dot at an arrow (
Hck2
to2Hck
to2Hck to1Hck
) means +. ) means -. ) indicates the start of measurement.
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LCX020BK
Item Vst rise time Vst fall time VST Symbol trVst
Vst 10% trVst 6 50% 50% 50% 50%
Waveform
90% 90% 10% tfVst
tfVst
Vst data setup time
tdVst
Vst
Vck
Vst data hold time
thVst
tdVst 90% Vck 10% thVst 90% 10%
Vck rise time VCK Vck fall time
trVck
tfVck
trVckn 90% Enb
tfVckn 90%
Enb rise time Enb fall time Vck rise/fall to Enb rise time Horizontal video period end to Enb fall time
trEnb tfEnb
10%
10%
tfEn
Horizontal video period
trEn
Horizontal blanking period
toEnb
ENB
Vck
50%
tdEnb
Enb toEnb 50% 50% toPcg
tdEnb 50%
Enb fall to Pcg rise time
toPcg
Pcg 6
Pcg rise time Pcg fall time PCG7 Pcg rise to Vck rise/fall time Pcg pulse width Blk rise time Blk fall time BLK Blk fall to Vst rise time Blk pulse width
trPcg tfPcg toVck trPcg twBlk tfBlk toVst twBlk
Vck toVck 50% Pcg 6 Vst
50%
50% twPcg
50%
Blk 50% 6
50% twBlk toVst
7 Input the pulse obtained by taking the OR of the above pulses and BLK to the PCG input pin. -9-
LCX020BK
Electrical Characteristics (Ta = 25C, HVDD = 15.5V, VVDD = 15.5V) 1. Horizontal drivers Item Input pin capacitance HCKn HST Input pin current HCK1 HCK2 HST RGT Video signal input pin capacitance Current consumption Csig IH Symbol CHckn CHst Min. -- -- -500 Typ. Max. Unit 8 8 -110 13 13 -- -- -- -- 270 pF pF A A A A pF mA HCKn: HCK1, HCK2 (4.8MHz) HCK1 = GND HCK2 = GND HST = GND RGT = GND Condition
-1000 -350 -500 -150 -- -- -180 -30 150
16.0 30.0
2. Vertical drivers Item Input pin capacitance VCK VST Input pin current VCK Symbol Min. CVck CVst -- -- Typ. Max. Unit 8 8 13 13 -- -- 5.0 pF pF A A mA VCK = GND PCG, VST, ENB, DWN, BLK, MODE1, MODE2, MODE3 = GND VCK: (24.9kHz) Condition
-1000 -160 -150 IV -- -30 3.0
PCG, VST, ENB, DWN, BLK, MODE1, MODE2, MODE3 Current consumption
3. Total power consumption of the panel Item Symbol Min. -- Typ. Max. Unit 300 600 mW
Total power consumption of the panel PWR (MAC16)
4. Pin input resistance Item Pin - Vss input resistance Symbol Min. Rpin 0.4 Typ. 1 Max. Unit -- M
5. Uniformity improvement signal input capacitance Item Symbol Min. -- Typ. 7 Max. Unit 16 nF
Uniformity improvement signal input CPSIGon capacitance
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LCX020BK
Electro-optical Characteristics Item Contrast ratio Optical transmittance R X Y Chromaticity G X Y B X Y V90 V-T characteristics 25C 60C V50 25C 60C V10 Half tone color reproduction range ON time Response time OFF time Flicker Image retention time 25C 60C R-G B-G 0C 25C 0C 25C 60C 60 min. 25C 60C Symbol CR25 CR60 T Rx Ry Gx Gy Bx By V90-25 V90-60 V50-25 V50-60 V10-25 V10-60 V50RG V50BG ton0 ton25 toff0 toff25 F YT60 7 8 6 5 4 3 2 Measurement method 1 Min. 40 40 0.85 0.560 0.300 0.260 0.541 0.120 0.040 0.9 1.0 1.2 1.3 1.9 1.8 -- -- -- -- -- -- -- --
(Ta = 25C, NTSC mode) Typ. 70 70 1.0 Max. -- -- -- % Unit --
0.600 0.670 0.360 0.410 0.300 0.350 CIE 0.595 0.650 standards 0.148 0.187 0.148 0.187 1.4 1.6 1.8 1.9 2.4 2.3 -0.10 0.05 20 14 45 35 -- -- 2.0 2.2 2.4 2.5 3.0 3.0 0.25 0.45 100 40 150 70 -40 20 dB s ms V V
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LCX020BK

Basic measurement conditions (1) Driving voltage HVDD = 15.5V, VVDD = 15.5V VVC = 7.0V, Vcom = 6.6V (2) Measurement temperature 25C unless otherwise specified. (3) Measurement point One point in the center of the screen unless otherwise specified. (4) Measurement systems Two types of measurement system are used as shown below. (5) Video input signal voltage (Vsig) Vsig = 7.0 VAC [V] (VAC = signal amplitude) Measurement system I
Back Light
Luminance Meter 3.5mm LCD panel
Measurement Equipment
Back light: color temperature 6800K 700K (25C) Back light spectrum (reference) is listed on another page.
Measurement system II
Optical fiber Light receptor lens Light Detector Measurement Equipment
Drive Circuit
LCD panel
Light Source
1. Contrast Ratio Contrast Ratio (CR) is given by the following formula (1). CR = L (White) ... (1) L (Black)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V. L (Black): Surface luminance of the panel at VAC = 4.5V. Both luminosities are measured by System I. - 12 -
LCX020BK
2. Optical Transmittance Optical Transmittance (T) is given by the following formula (2). T= L (White) x 100 [%] ... (2) Luminance of Back Light
L (White) is the same expression as defined in the "Contrast Ratio" section. Optical transmittance is measured by System I. 3. Chromaticity Chromaticity of the panel is measured by System I. Raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. System I uses x and y of the CIE standards as the chromaticity here. Signal amplitudes (VAC) supplied to each input R input R Raster G B 0.5 4.5 4.5 G input 4.5 0.5 4.5 B input 4.5 4.5 0.5 (Unit: V) 4. V-T Characteristics V-T characteristics, or the relationship between signal amplitude and the transmittance of the panel, are measured by System II by inputting the same signal amplitude VAC to each input pin. V90, V50, and V10 correspond to each voltage which defines 90%, 50%, and 10% of transmittance respectively.
Transmittance [%]
90
50
10 V90 V50 V10
VAC - Signal amplitude [V]
5. Half Tone Color Reproduction Range The half tone color reproduction range of the LCD panel is characterized by the differences between the V-T characteristics of R, G and B. The differences of these V-T characteristics are measured by System II. System II defines signal voltages of each R, G and B raster mode which correspond to 50% of transmittance, V50R, V50G and V50B respectively. V50RG and V50BG represent the differences between V50R and V50G and between V50B and V50G, and are given by the following formulas (3) and (4) respectively. V50RG = V50R - V50G ... (3) V50BG = V50B - V50G ... (4) - 13 -
100
V50RG V50BG
Transmittance [%]
50 R raster
G raster B raster
0
V50R V50B V50G VAC - Signal amplitude [V]
LCX020BK
6. Response Time Response time ton and toff are defined by formulas (5) and (6) respectively. ton = t1 - tON ... (5) toff = t2 - tOFF ... (6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. The relationships between t1, t2, tON and tOFF are shown in the right figure.
Input signal voltage (Waveform applied to the measured pixels)
4.5V 7.0V
0.5V
0V
Optical transmittance output waveform 100% 90%
10% 0%
tON
t1 ton
tOFF
t2 toff
7. Flicker Flicker (F) is given by the formula (7). DC and AC (MAC16/SVGA/VGA/PC98/NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the panel output signal for gray raster mode are measured by a DC voltmeter and a spectrum analyzer in System II. F [dB] = 20log { AC component } ... (7) DC component R, G, B input signal voltage for gray raster mode is given by Vsig = 7.0 V50 [V] where: V50 is the signal amplitude which gives 50% of transmittance in V-T curve.
8. Image Retention Time Image retention time is given by the following procedures. Apply a monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale of Vsig = 7.0 VAC [V] (VAC: 3 to 4V) so as to give the maximum image retention. Hold input signal VAC. The time for the residual image to disappear gives the image retention time. Monoscope signal conditions Vsig = 7.0 4.5 or 7.0 2.0 [V] (shown in the right figure) Vcom = 6.6V
4.5V 2.0V 7.0V 2.0V 4.5V
Black level White level
0V Vsig waveform
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LCX020BK
Example of Back Light Spectrum (Reference)
Spectral distribution data
5.000E - 01
A.U.
0.000E + 00 300.00 Wavelength [nm]
800.00
- 15 -
1. Dot Arrangement RGB dots are arranged in a stripe pattern. The shaded area is used for the dark border around the display.
Gate SW
Gate SW
Gate SW
Gate SW
Gate SW
Gate SW
R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
R1
G1
B1
R2
G2
B2
R3
G3
B3
R4
G4
B4
R5
G5
B5
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
R1
G1
B1
R2
G2
B2
R3
G3
B3
R4
G4
B4
R5
G5
B5
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 G6 B6
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
Active area B5 R6
R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 B5 R6 G6 B6 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
48 dots 2592 dots
2496 dots (effective 14.23mm)
48 dots
2 dots
G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R1 G1 B1 R6 G6 B6 R1 G1 B1 R6 G6 B6
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Photoshielding
G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 G4 B4 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6 R1 G1 B1 R2 G2 B2 R3
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
R5
G5
B5
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
R5
G5
B5
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
624 dots (effective 10.61mm)
G4 B4 R5 G5 B5 R6 G6 B6 R1 G1 B1 R6 G6 B6 R1 G1 B1 R6 G6 B6 R5 G5 B5 R6 G6 B6 R1 G1 B1 R6 G6 B6 R1 G1 B1 R6 G6 B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
628 dots
R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
R1
G1
B1
R2
G2
B2
R3
G3
B3
R4
2 dots
R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 G5 B5 R6 G6 B6
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
R1
G1
B1
R2
G2
B2
R3
G3
B3
R4
G4
B4
R5
G5
B5
R6
G6
B6
R1
G1
B1
R6
G6
B6
R1
G1
B1
R6
G6
B6
LCX020BK
LCX020BK
2. LCD Panel Operations [Description of basic operations] * A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 624 gate lines sequentially in every single horizontal scanning period. (in Macintosh16 mode) * A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits, applies selected pulses to every 2496 signal electrodes sequentially in a single horizontal scanning period. These pulses are used to supply the sampled video signal to the row signal lines. * Vertical and horizontal shift registers address one pixel, and then Thin Film Transistors (TFTs; two TFTs for one dot) turn on to apply a video signal to the dot. The same procedures lead to the entire 2496 x 832 dots to display a picture in a single vertical scanning period. * The data and video signals shall be input with polarity-inverted system in every horizontal cycle.
[Description of operating mode] The LCD panel can change the angle of view by displaying a black frame to support various signal systems. The angle of view is switched by MODE1, 2 and 3. However, the picture center does not change. The angle of view mode settings are shown below. MODE1 L L L L H H MODE2 L L H H L L MODE3 L H L H L H Display mode Macintosh16: 832 x 624 SVGA: 800 x 600 PAL: 762 x 572 VGA/NTSC: 640 x 480 PC98: 640 x 400 WIDE: 832 x 480
The LCD panel has the following functions to easily apply to various uses, as well as various signal systems. * Right/left inverse mode * Up/down inverse mode These modes are controlled by two signals (RGT and DWN). The right/left and up/down mode settings are shown in the tables below. RGT H L Mode Right scan Left scan DWN H L Mode Down scan Up scan
Right/left and up/down mean the direction when the Pin 1 marking is located at the right side with the pin block facing upward. Since the display area is located in the center of the panel in each mode, the start pulse, clock phase and polarity for both the H and V systems must be varied. The phase relationship between the start pulse and the clock for each mode is shown on the following pages.
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LCX020BK
(1) Vertical direction display cycle (1.1) Macintosh 16
VD VST (DWN = H) VST (DWN = L) VCK 1 2 3 4 621 622 623 624
Vertical display cycle 624H
(1.2) SVGA
VD VST (DWN = H) VST (DWN = L) VCK 1 2 3 4 597 598 599 600
Vertical display cycle 600H
(1.3) PAL
VD VST (DWN = H) VST (DWN = L) VCK 1 2 3 4 569 570 571 572
Vertical display cycle 572H
(1.4) VGA/NTSC, WIDE
VD VST (DWN = H) VST (DWN = L) VCK 1 2 3 4 477 478 479 480
Vertical display cycle 480H
(1.5) PC98
VD VST (DWN = H) VST (DWN = L) VCK 1 2 3 4 397 398 399 400
Vertical display cycle 400H
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LCX020BK
(2) Horizontal direction display cycle (2.1.1) Macintosh 16, WIDE, RGT = H
HD HST
HCK1 HCK2
1
2
3
4
137 138 139 140
Horizontal display cycle
(2.1.2) Macintosh 16, WIDE, RGT = L
HD HST
HCK1 HCK2
1
2
3
4
137 138 139 140
Horizontal display cycle
(2.2.1) SVGA, RGT = H
HD HST HCK1 HCK2 1 2 3 4 131 132 133 134
Horizontal display cycle
(2.2.2) SVGA, RGT = L
HD HST HCK1 HCK2 1 2 3 4 131 132 133 134
Horizontal display cycle
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LCX020BK
(2.3.1) PAL, RGT = H
HD HST HCK1 HCK2 1 2 3 4 125 126 127 128
Horizontal display cycle
(2.3.2) PAL, RGT = L
HD HST HCK1 HCK2 1 2 3 4 125 126 127 128
Horizontal display cycle
(2.4.1) VGA/NTSC/PC98, RGT = H
HD HST HCK1 HCK2 1 2 3 4 105 106 107 108
Horizontal display cycle
(2.4.2) VGA/NTSC/PC98, RGT = L
HD HST HCK1 HCK2 1 2 3 4 105 106 107 108
Horizontal display cycle
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LCX020BK
3. 18-dot Simultaneous Sampling The horizontal shift register performs SIGR1 to SIGR6, SIGG1 to SIGG6 and SIGB1 to SIGB6 signal sampling simultaneously, which requires phase matching between each signal to prevent the horizontal resolution from deteriorating. Phase matching by an external signal delaying circuit is needed before applying video signals to the LCD panel. The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following phase relationship diagram indicates the phase setting for right-direction scanning (RGT = High level). For leftdirection scanning (RGT = Low level), the phase settings should be inverted for the SIGR1 to SIGR6, SIGG1 to SIGG6 and SIGB1 to SIGB6 signals.
SIGR1, SIGG1, SIGB1 SIGR2, SIGG2, SIGB2
S/H CK1 S/H CK2
S/H S/H
SIGR1, SIGG1, SIGB1 SIGR2, SIGG2, SIGB2
SIGR3, SIGG3, SIGB3 SIGR4, SIGG4, SIGB4
S/H CK3 S/H CK4
S/H S/H
SIGR3, SIGG3, SIGB3 SIGR4, SIGG4, SIGB4
SIGR5, SIGG5, SIGB5 SIGR6, SIGG6, SIGB6
S/H CK5
S/H S/H CK6
SIGR5, SIGG5, SIGB5 SIGR6, SIGG6, SIGB6
(right-direction scanning)
HCKn CK1 CK2 CK3 CK4 CK5 CK6
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LCX020BK
LCX020BK
Display System Block Diagram An example display system configuration is shown below.
R CXA2112R
R G B CXA2111R
G CXA2112R LCX020BK
B CXA2112R
HSYNC
PLL
MCK
FRP CXD3500R VSYNC TIMING PULSE
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LCX020BK
Notes on Handling (1) Static charge prevention Be sure to take the following protective measures. TFT-LCD panels are easily damaged by static charges. a) Use non-chargeable gloves, or simply use bare hands. b) Use an earth-band when handling. c) Do not touch any electrodes of a panel. d) Wear non-chargeable clothes and conductive shoes. e) Install conductive mats on the working floor and working table. f) Keep panels away from any charged materials. g) Use ionized air to discharge the panels. (2) Protection from dust and dust a) Operate in a clean environment. b) When delivered, panel surface (Polarizer) is covered by a protective sheet. Peel off the protective sheet carefully so as not to damage the panel. c) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave a stain on the surface. d) Use ionized air to blow dust off the polarizer. (3) Other handling precautions a) Do not twist or bend the flexible PC board especially at the connecting region because the board is easily deformed. b) Do not drop the panel. c) Do not twist or bend the panel or panel frame. d) Keep the panel away from heat sources. e) Do not dampen the panel with water or other solvents. f) Avoid storing or using the panel at a high temperature or high humidity, which may result in panel damages.
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LCX020BK
Package Outline
Unit: mm
18.0 0.3 12.0 0.05
Thickness of the connector
0.2 0.03
2
electrode
5.0 0.3
1
(26.0)
47.75 0.9
3
Polarizing Axis
Incident light
Active Area
63 93
0.3 0.3
0.05 0.3
4
0.8 0.1 1.9 0.3 2.33 0.4
4
(14.227) 17.6 0.3 19.65 0.15 0.3 0.3 19.75 0.15
2.761 0.1 1.075 0.3 0.05 0.3
No
P 0.6 0.02 x 19 = 11.4 0.03 P 0.6 0.02 x 18 = 10.8 0.03 0.3 0.07 0.6 0.07
Description FPC Reinforcing board Reinforcing material Polarizing film weight 2g
1 2
PIN1
PIN 39
3 4
electrode (enlarged)
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Reinforcing material 1.5 1.0
1.754 0.1
14.0 0.3
(10.608)
18.25 0.15
19.75 0.15

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